CNTFET-based divide-by-N/[N+1] DMFPs using m-GDI method for future generation communication networks

To decrease the parameters like: power dissipation, propagation delay and chip area in very-large-scale integration (VLSI) circuits, the gate-diffusion input (GDI) technique is convenient to be used. One of the most important functional blocks in frequency synthesizers is the dual-modulus frequency prescaler (DMFP) circuit. In this research work, we present novel powerful and robust designs which are part of proposed divide-by-N/[N+1] DMFP schemes for moduli set {N=1,2,3,4} with more efficiency, power storing and minimizing the gate counts using carbon nano-tube field-effect transistor (CNTFET)-based modified GDI (m-GDI) method. The simulation results of architectures in two standard CMOS and CNTFET technologies, clarified that the CNTFET-based proposed circuits are more effective in terms of critical path delay, power dissipation and worst delay-power consumption-chip area product (DPA) parameters. Also, according to the simulation results, presented DMFPs are capable to work at extensive evaluate frequency ranges with higher figure of merits (FOMs) at the maximum operating frequency (fmax.). For the proposed circuit's performance different variations process including diameter of CNTs, voltage and temperature (PVT) have been done by Monte-Carlo simulations. Thus, comparative analysis based on the Monte-Carlo simulation exhibits that the proposed structures show significant low-power consumption, sensitivity and larger noise-immunity in the presence of the impact of PVT variations. Therefore, the proposed DMFPs can be implemented in digital phase-locked loop (PLL) blocks for future wireless communication like: 5 Generation (5G) and microprocessor chips.