Low-cost methodology for fault diagnosis and localization in pipelined ADCs

This paper presents two low cost methodologies for fault diagnosis and localization in digitally calibrated pipelined analog-to-digital converters (ADCs). A simple design for test (DFT) is proposed to generate the required test stimulus and to provide the required controllability to collect the code error (fault) signature, which is represented by the difference between the transfer characteristics of the device under test and a golden one. In the first method, the features of the code error-signature are modeled to differentiate between the fault types and fault locations. The main focus of the first method is to detect and localize the capacitance mismatch, gain degradation, reference voltage error and offset voltage error of the device under test (DUT). The modeled features of the code error signatures are the number of zero crossing and the number of jumps in its derivative. The number of zero crossing is utilized to diagnose and localize the capacitance mismatch and gain degradation faults, while the number of jumps is used to detect and localize the reference voltage and offset voltage faults. The faults are determined stage-wise. The second method needs longer diagnosing time, but is able to diagnose the multi-source faults. To verify the proposed methodologies, a ten-stage digitally-calibrated pipelined ADC is behaviorally modeled and simulated using MATLAB. Faults having different type and values are intentionally injected in different stages of the design. The simulation results show the effectiveness of the proposed methods in detecting the faulty portion and fault type. Therefore, the faulty (or even the weak) portion(s) of the DUT can be identified. Which is useful feedback information for the designer to enhance the reliability of the subsequent design generation.