Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme

An on-chip impedance self calibration methodology for LVSTL (low voltage swing termination logic) for LPDDR4 (low power double data rate) application is proposed. The proposed calibration is to compensate mismatches and variations of the transmitter output drivers due to process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect and compensate the transistor mismatches of the output driver due to process and temperature variations. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a 180 nm CMOS technology, and the impedance calibration technique is demonstrated with various external termination resistance of 40/48/60/80/120/240 Ω. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to adaptively control the gain factor of the receiver. The active area including power-ring of the transmitter is 0.48 mm2 with 0.14 mm2 of the proposed calibration circuit. Since there are 32 transceivers for two channels and the channels share the calibration circuits on the same DRAM die, the area overhead is less than 1.5%. The power consumption of the calibration circuits is 160 μW with 1.8 V power supply at 180 nm CMOS technology node.