Dynamic power estimation using Transaction Level Modeling

Designing an efficient (from performance and power points of view) system on chip (SoC) is one of the main challenges nowadays. This paper introduces a methodology that uses Transaction Level Modeling (TLM) to accelerate the simulation time for power estimation allowing fast SoC evaluation. Different modeling techniques are used to develop the proposed Transaction Level Power Modeling (TLPM) methodology. The methodology exploits abstracting the design using TLM. This abstraction allows fast simulation with still accurate functionality of the developed model. The methodology enables estimating power dissipation of real applications running on the SoC with high accuracy. ZYNQ-7000 platform is implemented on RTL and TLM to validate the methodology. The validation of the functionality is obtained through identical scenarios on both TLM and RTL. Experimental results reveal the efficiency and accuracy of the TLPM. The proposed methodology speeds up the simulation time by more than two orders of magnitude over RTL while the error in power estimation is less than 3%.