|کد مقاله||کد نشریه||سال انتشار||مقاله انگلیسی||ترجمه فارسی||نسخه تمام متن|
|4951501||1364360||2018||15 صفحه PDF||سفارش دهید||دانلود کنید|
- New Hardware Trojan (HT) that injects faults to create a denial-of-service attack.
- Heuristic-based fault detection model to diagnose faults and discover HTs.
- Link obfuscation for HT detection and graceful network degradation.
- Optimized AMD encoding to detect faults for continual use of a HT compromised link.
As Multiprocessor System-on-Chips (MPSoCs) continue to scale, security for Network-on-Chips (NoCs) is a growing concern as rogue agents threaten to infringe on the hardware's trust and maliciously implant Hardware Trojans (HTs) to undermine their reliability. The trustworthiness of MPSoCs will rely on our ability to detect Denial-of-Service (DoS) threats posed by the HTs and mitigate HTs in a compromised NoC to permit graceful network degradation. In this paper, we propose a new light-weight target-activated sequential payload (TASP) HT model that performs packet inspection and injects faults to create a new type of DoS attack. Faults injected are used to trigger a response from error correction code (ECC) schemes and cause repeated retransmission to starve network resources and create deadlocks capable of rendering single-application to full chip failures. To circumvent the threat of HTs, we propose a heuristic threat detection model to classify faults and discover HTs within compromised links. To prevent further disruption, we propose several switch-to-switch link obfuscation methods to avoid triggering of HTs in an effort to continue using links instead of rerouting packets with minimal overhead (1-3 cycles). To sustain data integrity over a compromised link, we propose an optimized implementation of algebraic manipulation detection (AMD) codes to detect any fault injection in targeted flits. Our proposed modifications complement existing fault detection and obfuscation methods and only add 2% in area overhead and 6% in excess power consumption in the NoC micro-architecture.
Journal: Journal of Parallel and Distributed Computing - Volume 111, January 2018, Pages 24-38