کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
4953737 1443117 2018 6 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A low power and small area digital self-calibration technique for pipeline ADC
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
A low power and small area digital self-calibration technique for pipeline ADC
چکیده انگلیسی

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm2, respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 83, January 2018, Pages 52-57
نویسندگان
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