A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

This paper presents a 7-bit 15 × interleaved SAR ADC that operates up to 3 GS/s, using 180 nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2 bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7 bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2 C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits) > 6.5-bit and SFDR (Spur Free Dynamic Range) = −52.8 dBc for a single SAR converter with sampling at 200 MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR = −45 dBc with sampling at 3 GS/s up to Nyquist frequency. This ADC consumes 150 mW at 1.8 V supply and achieves a Figure-of-Merit (FoM) of 700 fJ/conv-step.