کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4971206 | 1450460 | 2017 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A 0.3 V 8-bit 8.9Â fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
An 8-bit 10Â kS/s 0.3Â V ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC merged switching scheme reducing the switch energy by 98.4% compared with conventional switching architecture, the energy consumption of the SAR ADC is decreased drastically. Furthermore, a presented double-bootstrapped switch with leakage reduction technologies improves sampling linearity under 0.3Â V. In addition, to relieve non-linearity, boost technique is introduced in digital-to-analog converter (DAC) driving switch. The proposed ADC has been fabricated in 180Â nm 1.8Â V CMOS process. The measurement results show that effective number of bits (ENOB) of the ADC is 7.21Â bit at the Nyquist input frequency and 0.3Â V supply voltage, achieving a figure-of-merit (FOM) of 8.9 fJ/conversion-step. The chip area is 0.084Â mm2.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 68, October 2017, Pages 44-54
Journal: Microelectronics Journal - Volume 68, October 2017, Pages 44-54
نویسندگان
Wei Guo, Zhangming Zhu,