A simulated annealing algorithm for zoning in planning using parallel computing

• A simulated annealing heuristic that optimizes the delimitation of land use categories on cadastral parcel maps.
• The heuristic uses plot polygons instead of grid cells, which is more convenient, but involves more computational complexity.
• The objective function is based on suitability and compactness criteria. It generalizes previous proposals.
• The quality of the results for real situations is comparable to the quality of those obtained by experts.
• A parallel version that produces good results in terms of speed-up is proposed. It is suited for multicore processors.

There is an increasing demand for tools that support land use planning processes, particularly the design of zoning maps, which is one of the most complex tasks in the field. In this task, different land use categories need to be allocated according to multiple criteria. The problem can be formalized in terms of a multiobjective problem. This paper generalizes and complements a previous work on this topic. It presents an algorithm based on a simulated annealing heuristic that optimizes the delimitation of land use categories on a cadastral parcel map according to suitability and compactness criteria. The relative importance of both criteria can be adapted to any particular case. Despite its high computational cost, the use of plot polygons was decided because it is realistic in terms of technical application and land use laws. Due to the computational costs of our proposal, parallel implementations are required, and several approaches for shared memory systems such as multicores are analysed in this paper. Results on a real case study conducted in the Spanish municipality of Guitiriz show that the parallel algorithm based on simulated annealing is a feasible method to design alternative zoning maps. Comparisons with results from experts are reported, and they show a high similarity. Results from our strategy outperform those by experts in terms of suitability and compactness. The parallel version of the code produces good results in terms of speed-up, which is crucial for taking advantage of the architecture of current multicore processors.