Comments on “Dual-rail asynchronous logic multi-level implementation”

• Comments on “Dual-rail asynchronous logic multi-level implementation” are provided.
• Incorrect interpretation of disjoint sum-of-products (DSOP) form is clarified.
• Possibility for the occurrence of deadlock condition is elucidated.
• Problems with completion detection are described.
• Naïve and incorrect decomposition of NAND gates in the function block is explained.

In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148–159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.