Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities. The driver has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality. A mixed signal approach that detects and compensates for NMOS and PMOS transistor resistance variation is presented. An analog circuit detects the driver's resistance variation, and a digital circuit controls an analog compensation circuit to maintain line impedance matching for all signal conditioning configurations of the driver. When maximum signal conditioning is enabled, the driver can transmit a 40 Gbits/sec PRBS7 signal through a 10 in. FR4 channel. It achieves a differential eye-opening amplitude of 100 mVppd and an eye-opening width of 0.8 UI consuming 9.7 mW of at-speed power. Simulations demonstrate that worst case impedance deviation from 50 Ω due to process, voltage and temperature variation is 2.7%. The driver is designed in 28 nm CMOS process using a 0.85 V nominal supply voltage. It is simulated using HSPICE circuit simulator and mixed mode simulations tools.