IAE Optimization of PID Control Loop with Delay in Pole Assignment Space

The aim of the paper is to compare the results of tuning the PID control loop with delay performed by means of the IAE optimization technique and the dominant pole placement. Both these approaches are based on quite distinct requirements but their application results in control loop behaviour patterns not much different from each other. To obtain a generalized view of this comparison the control loop model is formulated in dimensionless variables resulting from the physical similarity point of view and the optimization procedure is carried out in the pole assignment coordinates. The point of view of the dominant poles is followed in the IAE optimization as well and the dominance proof is provided by means of a novel criterion based on the argument increment rule. The study is devoted to the disturbance rejection ability of the PID control loop.