Integration aspects of strained Ge pFETs

Strained Ge channel PFETs have the potential to outperform state-of-the-art strained Si channel PFETs. This paper describes the integration aspects for strained Ge channel devices based on TCAD simulations and experimental observations. The most scalable way of introducing channel stress is by the use of Si1−xGex strain relaxed buffers (SRB) and/or high Ge-content source/drain stressors, selectively grown in STI. Reduction of the thermal budget, damage and Ge loss during subsequent processing are key to maintain the high strain in the Ge channel till the end of processing.