Impact of the hardened floating-point cores on HIL technology

The Hardware-In-the-Loop (HIL) technique is increasingly used for testing power electronics. FPGAs (Field-Programmable Gate Array) are becoming usual in this kind of emulation due to their acceleration capabilities. But even using FPGAs, it has not been possible to reach real time simulations when small integration steps are necessary (around 100 ns or lower) if floating-point representation is used. Fixed-point has been the solution, but at a high design effort cost. With the release of FPGAs with HFP (Hardened Floating-Point) cores - dedicated floating-point blocks implemented in silicon -, the minimum achievable simulation step decreases significantly. This paper presents a comparison between HFP cores, floating-point in programmable logic and fixed-point for HIL models. Results show that both HFP-based and fixed-point arithmetic achieve a simulation step around 10 ns for a full-bridge converter model. A comparison regarding resolution and accuracy is also presented, because acceleration is not the only issue when decreasing the integration step. Numerical resolution also plays an important role, and 32-bit floating-point representation finds a double barrier: acceleration marked by technology, and numerical resolution. Both are explored in this paper.