Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal-ferroelectric-oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO2/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C-V memory window was 6 V for metal-ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO2 buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.