A time efficient method for determination of static non-linearities of high-speed high-resolution ADCs

Static non-linearity tests on ADCs take many hours to complete, especially when they are of high-resolution, say, 10-bits or more. Efforts to reduce this test time have been attempted, but suggested methods are either not suitable for high-speed high-resolution ADCs or deviate from procedures given in relevant standards, viz. IEC 61083-1, IEEE 1057 or IEEE 1241. In this paper, a novel method is proposed to test such ADCs. It is simple, easy to implement, requires less time and does not impose any change to relevant standards. Instead of the conventional method of applying one DC waveform at a time to the ADC, the proposed method involves application of several DC waveforms (say, 32 or 64) at once, configured as a staircase waveform. Many staircases are used to cover the input voltage range. Thus, in a single acquisition, information corresponding to several DC waveform applications is generated. Hence, a reduction in test time is achieved. Generation of these staircases is straightforward using an arbitrary waveform generator. The timesavings achieved from this method depend on available memory and waveform uploading speed of the arbitrary waveform generator.