Architectures and design considerations for wireline ΣΔ modulators beyond ADSL

In this paper we discuss design considerations for sigma-delta modulators (ΣΔMs) aimed at high-linearity high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μm CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade ΣΔMs to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results.