A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation

In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, is proposed. Analytical models accounting for mobility degradation due to the vertical field, channel length modulation, drain induced barrier lowering and velocity saturation effects have been included in the model formulation. Also the action of parasitic bipolar transistor intrinsic to the SOI MOSFET has been considered. The proposed model considers the highly doped part of the GC transistor acting as a 'main' transistor, whose drain voltage is modulated by the remaining part of the channel. Experimental results and two-dimensional simulated data were used to test the model, by comparing the drain current and some important characteristics for analog circuit design, such as the transconductance over the drain current ratio and output conductance, achieving a good agreement in both cases.