| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 10411928 | Solid-State Electronics | 2005 | 5 Pages |
Abstract
A fully integrated gate stack structure with an additional stoichiometric silicon nitride layer in the control oxide referred to as “SNONOS” is used to improve the electrical performance of nitride-based memories. The process is completely compatible with conventional silicon processes. By employing the new structure, the detrimental “back-tunneling” effect is suppressed without sacrificing device capacitance. Thus, a threshold voltage improvement of approximately 1.2Â V is observed for the erase state. Retention for devices with similar erase performance is also improved with the SNONOS structure. Further mitigation of the “back-tunneling” effect is observed for devices with high work function gate material.
Keywords
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Jeong Hee Han, Ju Hyung Kim, Seung Hyun Lee, Chungwoo Kim,