Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10413348 | Solid-State Electronics | 2005 | 6 Pages |
Abstract
We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range â¼7-17Â nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300Â K and at 1.6Â K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9Â m2/VÂ s, which was measured from a 16.5Â nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.
Related Topics
Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
M. Prunnila, J. Ahopelto, F. Gamiz,