Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
1139490 | Mathematics and Computers in Simulation | 2013 | 17 Pages |
Abstract
In this paper a specific application is considered: the combined output current and capacitor voltage control of a 4-level flying-capacitor converter (FCC). This inverter topology possesses important advantages, but the control is also challenging. The high computational burden of MBPC is often restrictive for a good implementation. In this paper the implementation in a field-programmable gate array (FPGA) of an efficient prediction and optimization calculation core for finite-set MBPC is discussed. The core is fully implemented in programmable digital logic and a good performance is obtained by exploiting the strong points of the FPGA: parallelism and pipe-lining. The calculation core can be used in three applications: for hardware co-simulations, for hardware acceleration with processor-based implementations and for full FPGA implementations. Experimental results obtained with an FPGA implementation are presented.
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Authors
Thomas J. Vyncke, Steven Thielemans, Jan A.A. Melkebeek,