All inkjet-printed, fully self-aligned transistors for low-cost circuit applications

Layer-to-layer registration is a significant problem in printed electronics since parasitic overlap capacitances resulting from the poor registration of conventional printers substantially degrade device operating speeds. To overcome this, a novel inkjet printing process was utilized to demonstrate an all inkjet-printed and fully self-aligned transistor, as well as fully self-aligned inverters for the first time. Self-alignment of transistor source/drain electrodes to gates was achieved by a printed wetting-based roll-off process, resulting in an improved overlap capacitance as small as 0.14–0.23 pF mm−1. Circuit building blocks including transistor arrays and inverters were demonstrated using a novel self-split source/drain and a self-aligned interconnect printing technique. Due to the substantial reduction in overlap capacitance, demonstrated inverters showed a propagation delay as low as 0.488 ms at a fan-out of 1, despite using materials with mobility of 0.01 cm2 V−1 s−1, thus showing a performance that is suitable for use in a range of low-cost electronics applications, realized using a simple, scalable process.

Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slideResearch highlights► A novel inkjet printing process was utilized to realize self-alignment of source/drain to gate. ► All inkjet-printed, fully self-aligned transistors were demonstrated. ► The overlap capacitances of fully printed self-aligned transistors are as small as 0.14–0.23 pF mm−1. ► The all printed, fully self-aligned inverter has the propagation delay as low as 0.488 ms.