Application of lock-in thermography for failure analysis in integrated circuits using quantitative phase shift analysis

Lock-in thermography (LIT), which is a well established technique for non-destructive evaluation, can also be used to identify and locate thermal active electrically defects like shorts and resistive opens in microelectronic devices. Defect localization on the level of the integrated circuits (IC) requires a μm resolution. But LIT can also be applied to locate buried thermal active defects within fully packaged microelectronic devices by analysing the thermal signal detected at the surface of the device. In addition to the lateral localization of the hot spot, its depth can also be determined by analysing the phase shift of the thermal signal. This is especially valued for non destructive defect localization in complex 3D integrated system in package devices (3D SiP). In comparison to competitive thermal imaging techniques, like liquid crystal imaging or fluorescent micro thermal imaging, LIT is easier to apply since it does not need any foreign thermal sensitive layer at the surface of the device. Also, the sensitivity limit of this technique within μK range is significantly better. In addition the dynamic character of LIT reduces thermal blurring, and the problem of inhomogeneous IR emissivity can be overcome by using the phase image or the 0°/−90° image. The spatial resolution limit of the used microscopic thermal imaging setup performed in the mid-wavelength range is about 5 μm, but can be improved to 1.5 μm by applying solid immersion lenses. Within the paper, the principle theory of LIT and the practical use for both, single and multiple IC devices is presented.