Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO2/SiO2 gate dielectric stacks

In this work, we report on effects of post-deposition annealing on electrical characteristics of metal–insulator–semiconductor (MIS) structures with HfO2/SiO2 double gate dielectric stacks. Obtained results have shown the deterioration of electro-physical properties of MIS structures, e.g. higher interface traps density in the middle of silicon forbidden band (Ditmb), as well as non-uniform distribution and decrease of breakdown voltage (Ubr) values, after annealing above 400 °C. Two potential hypothesis of such behavior were proposed: the formation of interfacial layer between hafnia and silicon dioxide and the increase of crystallinity of HfO2 due to the high temperature treatment. Furthermore, the analysis of conduction mechanisms in investigated stacks revealed Poole–Frenkel (P–F) tunneling at broad range of electric field intensity.