Optimization of Si interface control layer thickness for high-k GaAs metal–insulator–semiconductor structures

This paper reports on a GaAs high-k MIS structure having an MBE-grown Si interface control layer (ICL) which has recently shown a promising result. It has a HfO2/SiNx/Si ICL/GaAs structure where an ultrathin SiNx buffer layer is produced by direct nitridation of Si ICL. In this study, a particular attention is paid to optimize the initial thickness of Si ICL by correlating the interface structure studied by in situ X-ray photoelectron spectroscopy with the electronic interface quality studied by capacitance–voltage measurements. It was found that the presence of ML-level Si ICL at the interface after the formation of the SiNx is vitally important to obtain low values of interface trap density (Dit). Excess initial thickness of Si ICL also resulted in increase of Dit. Initial Si ICL thicknesses of 5–6 MLs were found to be optimum, and gave U-shaped Dit distributions with minimum Dit values around 1 × 1011 cm−2 eV−1 or below.