The optimised spin-valve magnetotransistor

The paper presents a technique for the realization of a spin-valve transistor. Its semiconductor emitter (a field emitters array) and collector are realized on a (1 0 0) Si wafer and a metallic base is made up of several thin layers, alternatively magnetic and non-magnetic. This structure has the advantage of a higher Schottky barrier between the base and the emitter, compared to an emitter realized on monocrystalline Si wafer. For a single spin-valve (either inferior or superior), GMR ratios of 12% have been obtained; for a symmetric dual structure, GMR ratios were higher than 20%. The fabrication of the spin-valve transistor includes several original technological operations: (1) realization of multi-layer magnetic nanostructures with a high magneto-resistive ratio and a low number of defects at the interface; the base is realized on porous silicon substrate and is made of a nanostructured thin ferromagnetic (FM) layer alternating with thin non-ferromagnetic (NFM) ones, leading to very high variations of their electrical resistance under an external magnetic field. The width of each layer varies from 2 to 5 nm. (2) The emitter, an array made out of 3000 field emission vertical nanoemitters, is realized inside the drain of a MOSFET by reactive ion etching (RIE) and phosphor ionic implantation. The emission current increases in this case due to the current thermally generated in the depletion layer underneath the emitters and due to the electron current from the inversion layer underneath the MOSFET gate.