An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications

In this paper, we have proposed and simulated a new 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) MOSFETs for nanoscale digital circuit applications. The subthreshold electrical properties such as subthreshold current–voltage characteristics, subthreshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed. It has been observed that the DM design can effectively suppress short-channel effects as compared to single material gate structure. The proposed analytical expressions are used to formulate the objective functions, which are the pre-requisite of genetic algorithm computation. The problem is then presented as a multi-objective optimization one where the subthreshold electrical parameters are considered simultaneously. Therefore, the proposed technique is used to search of the optimal electrical and geometrical parameters to obtain better electrical performance of the 10-nm-scale transistor. These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.

► Novel 10-nm Dual-Material Surrounded Gate MOSFETs design is proposed. ► Introducing the DM design, improves the SCEs for digital applications. ► MOGAs-based approach is proposed to optimize the 10-nm-scale DMSG device. ► Optimized 10-nm-scale DMSG transistor is suitable for nanoscale logic applications.