Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

•Introduction to Asymmetric Underlap Double Gate NMOSFET with Gate Stack(A-U-DG-GS NMOSFET), with source side underlap.•Impact of variation of Lateral Straggle on the A-U-DG-GS NMOSFET.•Subthreshold Analog/RF Performance of A-U-DG-GS NMOSFET with varying Lateral Straggle.•Extraction of AC small signal parameters of A-U-DG-GS NMOSFET with varying Lateral Straggle using the Non Quasi Static (NQS) model of the A-U-DG-GS MOSFET.•Single stage amplifier analysis of the A-U-DG-GS NMOSFET.

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.