Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor

•Impact of drain doping profile on device electrostatics and circuit performance.•For analysis of circuit performance Verilog-A model has been developed.•The circuit level performance assessment is carried out by implementing inverter, common source amplifier, inverter amplifier and pseudo differential amplifier.

In this paper, for the first time, the impact of drain doping profile on device electrostatics and circuit performance of novel InAs/Si Hetero-junction Double Gate Tunnel Field Effect Transistor (H-DGTFET) has been investigated. A highly doped layer placed near the source and channel junction decreases the width of the depletion region, thus, improving the ON-current and circuit performance. For this purpose, the effects of drain doping profile on the analog/RF performance of H-DGTFET is studied in terms of transconductance (gm), parasitic capacitances, cut-off frequency (fT) and gain bandwidth (GBW) product. The value of fT is increased by 13.84% and the GBW is improved by 144.7% for GD profile in Drain with CL = 0.05 when compared to UD profile. Further, the impact of drain doping profile on the circuit performance has been investigated by implementing digital and analog/RF circuits most widely used for nanoelectronic applications. For this, Verilog-A model has been developed for InAs/Si H-DGTFET. The circuit level performance assessment is carried out by implementing inverter, common source amplifier, inverter amplifier and pseudo differential amplifier by using Complementary TFET (CTFET) technology in a Verilog-A environment.