Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

Bias instability of top-gate amorphous-indium–gallium–zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

► Gate bias instability of a-IGZO TFTs with source- and drain-offsets is studied. ► Instability is caused by migration of positive charges from/to offset regions. ► Recovery occurs without external excitation, dismissing defect creation/trapping. ► Appropriate drain and source bias-stresses either enhance or suppress instability. ► This verifies lateral ion migration to be the instability mechanism.