Design of Low Power Adaptive Pulse TriggeredFlip-Flop Using Modified Clock Gating Schemeat 90 nm Technology

In this paper, a novel low power adaptive pulse triggered flip-flop (PTFF) featuring exclusive-or gate based clock gating with replica path delay scheme is proposed. Clock gating is a very accepted technique to reduce dynamic power of idle clocking subsystems. Incorporating clock gating with PTFF leads to reduction in dynamic power consumption and replica path delay pulse generator simplifies design effort and achieves robust timing characteristics as compared to the conventional PTFF. The proposed PTFF features best power delay product performance. This scheme is implemented using CMOS 90 nm BSIM4 technology file in Synopsys HSPICE. Simulation results indicate that the proposed design excels conventional designs in performance metrics such as average power consumption, minimum D to Q delay, and power-delay-product. The average power consumption of the proposed design reduces by 51% as compared to replica-path pulse triggered flip-flop for 100% switching activity.