Stress measurements in tungsten coated through silicon vias for 3D integration

In 3D integration, interconnections between stacked dies are ensured by conductive through silicon vias. Electrical conduction is achieved via coating the vias sidewalls with a metal, such as tungsten. In this work we have compared thermal-dependent stress of thin tungsten films deposited either in full plate oron vias sidewalls. The comparison of stress measurements at room temperature and during heating cycles reveals large differences between full plate and vias samples. At room temperature, in the vias samples, the stress is a factor 4 less than it is in the full plate sample, with both values indicating a tensile stress. While a thermo-elastic behavior is expected for the full plate sample, no stress evolution as a function of temperature is observed in the case of the vias samples.

► Thermal stress of thin W films deposited on full plate or Through Silicon Vias (TSV). ► Modified sin2(ψ) method developed for stress measurements in W-coated TSV. ► Large stress difference between blanket films and TSVs observed at room temperature. ► Different evolutions of stress versus temperature in blanket films and TSVs.