Low temperature selective epitaxial growth of SiCP on Si(110) oriented surfaces

We demonstrate growth of SiCP film on Si(110) substrates with excellent structural quality, based on X-Ray Diffraction, Cross-sectional Transmission Electron Microscopy and Secondary Ion Mass Spectrometry analysis. This (110) surface orientation is very important since it represents the sidewall of recessed Source/Drain (S/D) areas when the film is used as an embedded stressor to induce uniaxial tensile strain in a planar transistor. An optimized (110) SiCP growth process can also be used to thicken the S/D regions of non-planar multi-gate device structures (e.g. Fin Field Effect Transistors, Tri-gate FETs) with a highly doped epitaxial film in order to enable good electrical contacts and/or induce strain. The films have been grown using Si3H8, SiH3CH3 and PH3 for growth and Cl2 as the etchant gas, all in inert carrier gas. H2 has been eliminated, preventing Cl2 from reacting with H2 yielding HCl, since Cl2 is needed to establish selectivity. We present trends on temperature, total pressure, SiH3CH3, PH3 and Cl2 etch flow. We studied selective epitaxial growth (SEG) in the 525–575 °C range. Thanks to the use of Si3H8 we can obtain high SEG rates even at 525 °C in conjunction with a high deposition pressure of 20 kPa (~ 150 Torr). It is observed that the growth rate, carbon concentration, phosphorous concentration and etch rate of SiCP on Si (110) differs greatly from that on Si (100). A process optimized specifically for Si(100) surfaces may yield no growth on Si(110) surfaces. However, optimizing a process on Si(110) is assured to result in growth on Si(100). Comparing one process optimized on Si(110) with the results on Si(100), we found a substantially lower SEG rate, higher [P] incorporation and lower [C] incorporation on Si(110). One key criterion for growth on patterned substrates with Si(110) sidewalls is that the SEG rate on the sidewall must be ≥ 0; otherwise the vertical sidewall will be etched and undercut of the spacer will occur, degrading the structural quality of the transistor and potentially impacting the electrical performance of the device.