Strain engineering of nanoscale Si MOS devices

The stress distribution in the Si channel regions of process-strained Si (PSS) MOSFETs with various widths and gate lengths was studied using TCAD process simulations. We show how these geometric effects can impact the achievable transistor performance gains. In this work, high-performance MOS devices have been achieved by stressors such as stressed SiN liner and S/D stressors such as SiGe alloy material and optimal geometric structure design. Strain engineering seems to be promising when considering mobility gain, carrier injection velocity, and ballistic efficiency of nanoscale MOS devices. This work helps the future MOS device design and demonstrates that strain engineering is important for future nanoscale device technology.