Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs

Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern deca-nanomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices.