Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
1674328 | Thin Solid Films | 2008 | 9 Pages |
Abstract
In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model.
Keywords
Related Topics
Physical Sciences and Engineering
Materials Science
Nanotechnology
Authors
Amit Sehgal, Tina Mangla, Mridula Gupta, R.S. Gupta,