Effect of Ti-rich TiN as a Co-salicide capping layer for 0.15 um embedded flash memory devices and beyond

This work is aimed at the practical effect of Ti-rich TiN as a Co-salicide capping layer on Gate-Induced Drain Leakage (GIDL) variation on High Voltage (HV) transistors in embedded Flash memory devices. It is reported that Ti-incorporating capping layer into Co film may reduce GIDL of HV transistor dramatically by ∼2 order magnitude of leakage at Vdd > 8 V of drain bias, resulting in better yield and reliability performance. This is due to the removal of contaminated silicon oxide from the reaction between diffused Ti and interfacial contaminated oxide at the Co/Si interface during salicide process. I–V measurement to define the leakage behavior and transmission electron microscopy (TEM) with element mapping analysis to investigate the Co/Si interface of S/D junction area have been carried out. Furthermore, we verified that Ti-rich TiN layer with the advantages of both Ti and TiN film could suppress GIDL with a larger process window due to the minimization of the sensitivity of Co-salicide process to Si-surface condition as well as provided a good junction leakage uniformity and contact resistance (Rc), concurrently.