Dielectric barriers, pore sealing, and metallization

Future high performance on-chip interconnect requires ultra-low K materials with an effective dielectric constant less than 2.0. Ultra-low K materials normally contain a certain degree of porosity. One of the key issues in the integration of porous materials is the inability of these materials to prevent gaseous penetration during the metallization process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this paper we describe a novel idea to seal the porous ultra-low K film using a thin Parylene layer deposited by a chemical vapor deposition technique. Interaction of metal barrier such as Ta and Ru with Parylene are explored. We found that Ta films deposited on Parylene surface exhibit the desirable alpha phase which has a bcc structure. We also found that Ta does not diffuse into Parylene films under a bias temperature stress of 0.5 MV/cm at 150 °C, but Ru does.