Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
1675367 | Thin Solid Films | 2006 | 4 Pages |
Abstract
To build Cu and low-k dielectric integrated MIM capacitor on standard CMOS silicon substrate for RFIC application, a Ta layer under the capacitor upper plate is necessary for preventing Cu diffusion into Si3N4 dielectric layer of capacitor. In the experiment, delamination was found after 1000 Å Ta film deposition on top of Si3N4. SEM inspection revealed that the delamination occurred at the interface between BD and Si3N4. The Ta/Si3N4 delamination was solved by inserting a SiO2 layer between BD and Si3N4 layers to compensate the stress difference between the BD and Si3N4/Ta stack films. Full process technology based on Cu and low-k process line for integrating passive device on silicon substrate was thus successfully developed.
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Physical Sciences and Engineering
Materials Science
Nanotechnology
Authors
M.B. Yu, Jiang Ning, S. Balakumar, V.N. Bliznetsov, G.Q. Lo, N. Balasubramanian, D.L. Kwong,