Creating a Self-configuring Finite State Machine out of Memory Look-up Tables

A finite state machine (FSM) is one of the most used digital logic applications in today's electrical systems. An FSM can be implemented in electrical systems based on programmable logic devices (PLD) or combinatorial logic platforms. Both platforms for a FSM contain advantages and restrictions for the hardware and software design. In regards of coding, FSM can be coded in alternatives styles and programming languages. In this paper we introduce the concept of a self-configuring FSM based on coding data as memory look-up tables. The resulting FSM is then able to self-configure the combinatorial logic of this FSM required to perform the compulsory state sequence. The primary benefit of using memory based look-up table (LUT) FSM is that well established data error correction methods can be applied to protect the FSM behavior, even in the event of single error events (SEE). A high level hardware design of this FSM will be presented in comparison to a PLD FSM implementation.