Low area 4-bit 5Â MS/s flash-type digitizer for hybrid-pixel detectors - Design study in 180Â nm and 40Â nm CMOS

We report on the design of a 4-bit flash ADC with dynamic offset correction dedicated to measurement systems based on a pixel architecture. The presented converter was manufactured in two CMOS technologies: widespread and economical 180 nm and modern 40 nm process. The designs are optimized for the lowest area occupancy resulting in chip areas of 160×55 µm2 and 35×25 µm2. The experimental results indicate integral nonlinearity of +0.35/−0.21 LSB and +0.28/−0.25 LSB and power consumption of 52 µW and 17 µW at 5 MS/s for the prototypes in 180 nm and 40 nm technologies respectively.