High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures previously described in the literature. Particularly care is given to optimize the Differential Non-Linearity (DNL) in order to obtain meaningful resolution figures that can be applied to the final applications. In the first implementation, based on a tapped delay line interpolator, the achieved resolution is in the 40–100 ps range. The hardware compensation for process voltage and temperature (PVT) variations, a weak point of FPGA designs, has been fully addressed by developing specific circuitry. Our hardware design allows closing a feedback loop for controlling the FPGA core voltage. PVT variations are therefore compensated by hardware in real time. The second implementation, based on a multiple-phase clock interpolator, the resolution is close to 175 ps. Interpolator DNL better than ±0.4 and ±0.2 LSB could be achieved. The relative advantages of both architectures are discussed within the scope of the foreseen applications.