Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
1830252 | Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment | 2008 | 6 Pages |
Abstract
130Â nm and 90Â nm CMOS processes are going to be used in the design of mixed-signal integrated circuits for the readout of detectors in the future generation of HEP experiments. In applications such as inner SLHC detectors, these ultra-deep submicron systems will have to stand total doses of ionizing radiation of the order of 100Â Mrad and beyond. While the scaling of the gate oxide thickness to about 2Â nm gives a high degree of radiation tolerance, issues such as the gate tunneling current and the sidewall leakage associated to lateral isolation oxides must be investigated. This paper provides an analysis of an extensive set of irradiation tests carried out on 130 and 90Â nm CMOS transistors belonging to commercial technologies. With special focus on the design of analog front-end circuits for silicon pixel and strip detectors, the impact of ionizing radiation on the noise performance is evaluated and the underlying physical degradation mechanisms are pointed out to provide criteria for improving radiation hardness properties.
Related Topics
Physical Sciences and Engineering
Physics and Astronomy
Instrumentation
Authors
Valerio Re, Luigi Gaioni, Massimo Manghisoni, Lodovico Ratti, Valeria Speziali, Gianluca Traversi,