An analog CMOS circuit for spiking neuron models

This paper proposes an analog CMOS circuit for spiking neuron models and shows the measurement results of the fabricated LSI which we have designed. The spiking neuron models express analog information by the timing of neuronal spike firing. Since these models operate asynchronously, it is expected that the spiking network operates faster than the conventional synchronous models. In the spiking neuron circuit, a postsynaptic potential (PSP) is generated by a switched-current source, and the spatio-temporal summation of PSPs is stored in a capacitor. Inverter chains with the predefined delay time generate a refractory period and a transmission delay for output spikes. The measurement results of the fabricated LSI demonstrate that the designed circuit operates correctly as a spiking neuron.