A New Low Leakage Power Flip-Flop Based on Ratioed Latches with Power Gating

This paper presents a new low leakage power flip-flop based on CMOS ratioed latches with the master-slave structure. Dual- threshold CMOS (DTCMOS) and channel length biasing leakage reduction techniques with power gating are used to reduce leakage power dissipations of the flip-flop. The simulation results show that the proposed flip-flop achieves considerable leakage reductions.