| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 5003175 | IFAC Proceedings Volumes | 2006 | 6 Pages |
Abstract
The paper presents new hardware solutions for bit-byte PLC CPU which are oriented on maximum utilisation of the capabilities of two-processor architecture of the CPU. The structure should enable the processors to work in concurrent mode as far as it is possible and minimise the situations, when one processor has to wait for the other. Every of the processors is an autonomous unit, that communicates with the other only for the purpose of process data exchange, required for proper operation of the CPU as a whole.
Keywords
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
Authors
Miroslaw Chmiel, Edward Hrynkiewicz,