Implementation of a modified Os-Cfar processor using FPGA technology

The main task of the radar is to make decisions without operator intervention. This decision is hampered by noise and interference. The Constant False Alarm Rate CFAR detector allows the radar to adjust its sensitivity while keeping the false-alarm rate reasonably constant. A CFAR based on an Ordered Statistic OS techniquc needs a large processing time, which limits its use. In this paper two modified OS-CFARs are proposed and their FPGA architectures are hierarchically implemented on Xilinx Virtex FPGA-XCV 1000-6 using the schematic option and functionality simulated using Xilinx foundation 2.1i. The results were compared with that obtained using MATIAB subroutines.