The Perm architecture approach: Supporting embedded system development

Despite of innovations in computer science software technology as high level languages, object-oriented programming, memory management units and operating systems with some security functions, software is still afflicted with the fault of a certain unreliability. Coarse-grained segment or page protection mechanism in hardware works with fix-sized memory blocks. A sufficient technique for a fine-grained protection mechanism down to a byte size resolution is still missing. This work has led to the new PERM (Protection Enhanced RISC Machine) processor architecture introducing a new approach to this problem. The load-store architecture of a RISC machine leads to a consistent realization of an enhanced address pointer procedure. This is combined with the ability to use much more information about the data objects and implements an effective data protection of all data in the processor's address range. This paper shows the effectiveness of the processor enhancement and gives some hints for its use inside embedded system development.