| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 5003228 | IFAC Proceedings Volumes | 2006 | 4 Pages |
Abstract
This article describes the implementation of a RocketIO bit-error rate tester (flERT) on the DSP custom hoard FD64x. The flER test is aimed at the serial link between two transceivers placed in the Virtex-I1 Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.
Keywords
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
Authors
Z. BradaÄ, S. Valach,