Investigation and process optimization of SONOS cell's drain disturb in 2-transistor structure flash arrays

The mechanism and distribution of drain disturb (DD) are investigated in silicon-oxide-nitride-oxide-silicon (SONOS) flash cells. It is shown that DD is the only concern in this paper. First, the distribution of trapped charge in nitride layer is found to be non-localized (trapped in entire nitride layer along the channel) after programming. Likewise, the erase is also non-localized. Then, the main disturb mechanism: Fowler Nordheim tunneling (FNT) has been confirmed in this paper with negligible disturb effect from hot-hole injection (HHI). And then, distribution of DD is confirmed to be non-localized similarly, which denotes that DD exists in entire tunneling oxide (Oxide for short). Next, four process optimization ways are proposed for minimization of DD, and VTH shift is measured. It reveals that optimized lightly doped drain (LDD), halo, and channel implant are required for the fabrication of a robust SONOS cell. Finally, data retention and endurance of the optimized SONOS are demonstrated.